• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A device for controlling electronic display and print elements for data output of electronic data acquisition equipment, non-automatic printers, cash registers, measurement printers and teletypes is designed for more economical generation of the current levels required for the display and print functions. The devices used for coding, transfer, and display of the output characters are also used to generate the required current levels. Luminescent or laser elements of a display and print matrix are driven intermittently by columns by a pulse train whose duty cycle is set by a microprocessor to one of two levels corresp. to display or print operations.
    公开号:SU976459A1
    申请号:SU787770169
    申请日:1978-04-25
    公开日:1982-11-23
    发明作者:Хорст Алерс；Гюнтер Альнох；Кристиан Диппман；Манфред Краус；Манфред Раух；Руди Шобер；Юрген Вальдманн；Вернер ШМИДТ；Эрнст Кучбах；Дитмар Фэльбер
    申请人:Феб Комбинат Роботрон (Инопредприятие)；
    IPC主号:
    专利说明:

    one
    The invention relates to devices for displaying and printing in electronic data collection devices, non-mechanical printing presses, registration offices, printing devices of measured values, teletypes and information processing systems in television engineering.
    23 39 285 describes a printing device in which a thermoelectric printing unit is controlled by a sequence of pulses, as in devices for indicating on LEDs used in electronic on-is
    desktop computing machines.
    When using this machine, the circuit (s for operating the device according to the patent DD 195 855.20
    CP M O B in which the luminescent elements are at the same time printed by Kwtii .v.H elements, it is necessary to change N; oui ocTb 11. puls B In the display and P part.
    The application of a known circuit in a computer is associated with additional costs, because separate control lines and control lines are required for controlling the display and printing elements.
    In addition, the electrical power, supplied by a series of pulses, is precisely metered by varying the duty cycle of HNmynbcoB. In this way, the circuit costs required to obtain a current of various POWER1 automatically increase.
    In addition to this, along with the nodes necessary for coding, transmission and image of the output data, according to E). The need for additional circuits to obtain the current of various strengths required for display and printing.
    The aim of the invention is to avoid additional costs for obtaining a current of various strengths.
    FIG. 1 depicts the proposed property; in fig. 2 and 3 - the algorithms of the device.
    The device contains (FIG. 1) an indication and printing matrix 1 consisting of semiconductor controllable elements 2. Semiconductor elements selected to represent a recording or printing line, which can be controlled simultaneously, sequentially, sequentially, sequentially, by row .
    In the example being described, sequential control is taken as the basis. The used semiconductor controlled elements 2 gfi control current of a certain force emit light, which provides light indication signs. Thermal printing of displayed characters is carried out. by increasing the current strength. In this case, the selected light-emitting semiconductor elements produce the additional heat required for printing. The lines of the display and printing matrix 1 are connected by a length of 3 parallel data transmissions to the print register 4, which is connected to the block 7 of the paratshelnoy data transmission and control 6 and is connected to the block 5 of the buffer memory 8. parallel transmission and also the control bus 9 10 is connected to the buffer storage unit 5. Bit register 10 is connected to bit decoder 11, which converts the digit entered into bit register 10 and assigned to one of the columns of the display and printing matrix 1 into the control signal of this column. Thus, the bit decoder 11 via the sampling bus 12 is connected to each column of the display and printing matrix 1. Both the parallel data transfer bus 3 and sample 12 passes through non-indicated logic circuits of the display and printing matrix 1, controlled by the bus 13 of block 5, which is connected via parallel data transfer bus 14 and data acquisition bus 15 to 15. the control bus 17, the buffer memory block 5 receives the control signals of the processor 16.
    The memory unit 18 and the random access memory unit 19 are connected via the data acquisition bus 15 by the processor 1c. Data exchange between block 18 and block 19 and the processor 16 is carried out using control lines 20 and 21. In addition, the second block 22 of the buffer memory is connected to the processor 16 via the control bus 23 and the parallel data line 24 of the GUD1 interface. The alphanumeric keyboard 26 is built on intersecting lines of words and columns, at the intersection points of which, depending on the set code, the corresponding key elements are triggered so that when a logical level arrives, for example, 1 on the word line, the bit is removed from the line of columns. a parallel sign corresponding to the input alphanumeric sign, which, through the input valve 27, transmits the second buffer memory block 22 via the parallel data transfer bus 28. The inlet valve 27 and the outlet valve 25 are opened by the second block 22 of the buffer memory through the control pins 29 and 30. Pressing the keyboard key 26 is communicated via the status bar 31 to the block 22 of the buffer memory and stored there (selector 1). This information remains in block 22 and is erased when it is polled by processor 16. New state record The key is pressed in block 22 of the buffer memory is possible after returning the key to its original position. The operation of the device is described by the example of a flowchart of the program. The program necessary for the implementation of this plan is recorded in memory block 18 or programmed and called command-line through process-, code 16. In addition to the program commands, block 18 also contains a sign generator with which the alphanumeric character entered into processor 16 is converted in a few columnar characters. Such a column mark includes parallel bits belonging to a single column of the display and printing matrix 1. The unspecified memory address register of the processor 16 serves to write the addresses of the column characters stored in the memory block 19. In accordance with operation 1 of the flowchart of the program, after starting the address memory register is set to a certain initial value. The state bus 32 polls the selector 1 of block 22 (test 2). This cycle repeats until the selector 1 is set to a conventional value as a result of pressing the key, for example, in. On the control bus 23 tires 16, the second buffer memory block 22 sends a keyboard polling signal 26, which is real 59764
    The unit 22 is connected via control busbars 29 and 30 and through the inlet and outlet valves 25 and 27 in the manner described above (step 3). The entered alphanumeric character is transmitted in parallel 5 in binary coded form to processor 16, then through block 18. this character is converted to the corresponding number of bit-parallel column characters that directly contain the alphanumeric character displayed in the display matrix 1 and print (operation 4). The transfer of these bit-parallel column characters into the corresponding memory cells of block 19 produces 5 seconds in a cycle with the corresponding addition g. the content of the address memory register is one (operation 6-9). Prior to the start of the display, the current contents of the memory address register is transferred to the auxiliary register of the processor 16, the memory address register is set to a certain initial value and the bit register Yu is also made to the initial state (start of the first 25 columns, steps 10-12). It is installed. The initial value is performed by the buffer 5 memory buffer, to which the corresponding signal-30 is sent from the 1G processor to the control women 17.
    In order to indicate the available data, the column characters, in accordance with the sequence from the input to the block 19 of the memory with random selection, reflect 35 with elements of the 2 corresponding columns 1 of the display and printing. Only selected elements 2 of the same column light up at the same time. Series-intermittent speaker control is performed at a frequency that provides the naked eye with an idea of the integrity of the image. On the control buses 17, the column memory mark prepared in the processor 16 is transmitted to the base 5 of the buffer memory. These signals are recorded by the control bus 6 and parallel data bus 7 by block 5 in memory register 4 (steps 13 or 13). The transition to the 50 branch, marked with a dash, depends on the inclusion of printing, for example through the selector 2 (test 15). This selector 2 is turned off when passing a predetermined number of items 55 and further print runs.
    Using the memory of the first command programmed in block 18, the
    96
    The output of the buffer memory unit 5: via control buses 17, outputs an enable signal to the control bus 13 (step 14 or 14). This SIGNSH1 switch-on opens the above-mentioned gates of the display and printing matrix 1, as a result of which both its strings, which are assigned to the binary values recorded in the print register 4, and the selected column are controlled. Thus, through the selected semiconductor elements 2 of the controlled column, the rising edge of the current pulse passes. The valves are constructed in such a way that they remain open until the second one, programmed in memory block 18, is closed by the Output command to shut down the operation (19 or 19). At this time, the maximum impulse TEC is flowing through the semiconductor controlled elements 2. Duration of control, i.e. the pulse duration is determined by the time interval between two commands, which depends on the number of runs of the programmed cycle memory block 18 (step 17 or 17, test 18 or 18). Since the commands are processed on a coherent basis, each cycle is based on a certain number of pulses of the clock generator of the processor 16,
    The number of runs can be set with integer values (indication qi) or -b-jj (indication and printing). As already indicated, each column of the display and printing matrix1 1 is controlled sequentially by a pulse, each of which is determined by the commands Enable Output and Disable Output. The time interval between pulses, the determined frequency, is set depending on the operations being processed and the tests performed before a new call to the Enable output command. At a constant frequency, the effective current strength is determined by the pulse duty cycle, which is determined by the values - (, g and -bj, the Value t / s is chosen so that the effective current applied to the semiconductor elements 2 is sufficient to excite the light emission, but would not form the heat required for thermal printing. In contrast, the pulse length resulting from -tp the resulting pulse duty ratio is chosen so that the effective current strength is sufficient for indication and for thermal printing, as opposed to indication, the state of sequential control of the columns during printing is held in the display and printing matrix 1 for a certain predetermined time, since otherwise the semiconductor elements 2 would generate too much heat (test 15).
    After each control of the column for subsequent excitation, light emission, the keyboard 26 is queried whether an input has been made (test 20). If new data is available for input, the indication is omitted and the entered character is transmitted starting from step 3 in the manner described above. For this, the contents of the auxiliary register, which has been incremented by one, is transferred to the memory address register (operation 24). If there is no new data entry, the count of the contents of the bit register 10 and the address memory register is increased by one (operations 22 and 23), which means that the selected semiconductor elements 2 of the next column are controlled. The subsequent counting of these registers is also carried out when performing a printing routine (operation 22 and. 23). If, after display or after writing, the address memory register reaches the value of the auxiliary register (test 21 or 21), then the control of the display and printing matrix 1 is restarted from the first column.
    At the same time, it is necessary that the maximum capacity of the address memory register in the location corresponds to the selected maximum
    the contents of the bit register 10. The state of the sequentially controlled columns during the operation mode of the Indicator passes through the system repeatedly until the printer is switched on again (test 15) or until the device is turned off. The scheme does not specify a software transition to disable (stop).
    The cost to regain intermittently sequential control justifies the use of a microprocessor, which is simultaneously used to obtain the two effective current values needed for this.
    / If a microprocessor or a central processor inclusive of the required memory is already present in the respective settings, then they may not be used to encode, transmit and image the output characters, as well as to obtain the specified current of various strengths.
    权利要求:
    Claims (1)
    [1]
    Invention Formula
    A display and printing device comprising a processor and a print register (connected to display elements and chapters & chats, characterized in that the print register 4 and the bit register 10 are connected to the buffer memory unit 5 that is connected to the data bus 15 and to the common control bus 23, wherein the buffer memory unit 5 comprises a decoder connected to the memory unit 18 and to the display and printing elements.
    It is recognized as an invention according to the results of the examination carried out by the Office for the Invention of the German Democratic Republic. Attacked
    Fig 1 data (dainy, addresses).
    The address memory register is set to a specific initial value.
    yes 5 help case register memory address register
    (t)
    Columnar gears
    AT
    not
    f is produced. SSob A selector 1)
    P ; f S RAM
    ZD
    Yes
    10 Conversion of the entered character S number of 5 params of 18 column characters in the keyboard Enter Keyboard output
    Memory Address Register Auxiliary Register
    Set a specific starting address 8 bit register
    AND
    A specific starting address S is assigned to the address memory reg ucfnpe.
    F
    FIG. 2
    0
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    同族专利:
    公开号 | 公开日
    DE2813640A1|1978-11-30|
    IT7822731D0|1978-04-26|
    IT1094535B|1985-08-02|
    SE7805892L|1978-11-27|
    DD131498A1|1978-06-28|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    JPS6123908B2|1978-12-26|1986-06-07|Intaanashonaru Bijinesu Mashiinzu Corp|
    GB2077970B|1980-02-26|1984-12-19|Teraoka Seikosho Kk|A label printer|
    DE3153381C2|1980-02-26|1994-02-10|Teraoka Seiko Kk|Printer for label giving weight, rate price and name|
    DE3507335C2|1984-03-01|1990-08-30|Canon K.K., Tokio/Tokyo, Jp|
    DE4009282C1|1990-03-22|1991-01-31|Gerhard Kurz|Hard copy maker for output data using paper or film - has mechanical-electric interface for printing unit and photocopying unit with structured plane light source and imaging system|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    DD7700199140A|DD131498A1|1977-05-26|1977-05-26|DEVICE FOR CONTROLLING ELECTRONIC DISPLAY AND PRINTING ELEMENTS FOR DATA DISTRIBUTION|
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